Low dropout (LDO) regulator design

LDO uses pmos as pass transistor. Why not nmos? If using nmos, output of the error amplifier op-amp applying on its gate may need to be very high, close to vdd. That makes such op-amp design difficult. When using pmos, the op-amp output is low, however, not to ground.

1) In light load (Iload is small), the pass pmos is working in saturation region;
2) When heavy load, the pass pmos may work in triode region, because Vgs has to be large to provide more current, and such  large Vgs may exceed Vds+Vth (both are fixed).

1) The dominant pole (p1) is usually inside the error amplifier op-amp, Miller frequency compensation formed by C or RC can be used, moving p1 to lower frequency, and/or providing a zero to cancel a pole's effect; p2 is usually at the LDO output; there is a high frequency pole due to the parasitic cap of pass pmos;
2) Alternatively, if the op-amp is one stage and/or does not have p1, frequency compensation can be done by putting C or RC across G and D of pass pmos, which can create p1. The parasitic caps inside op-amp thus create high frequency poles which are usually higher than p2, which is at the output of LDO.

Cload at the LDO output has a trade-off.
1) lager Cload can reduce the Vout ripple due to Iload switching;
2) smaller Cload moves p2 to higher frequency, making the LDO loop more stable.

PSRR over frequency usually has following shape:
1) at low frequency, PSRR is large negatively, e.g., -60 dB; the PSRR in this region is determined by the loop gain of LDO;
2) it rises to higher value in intermediate frequency, e.g., -20 dB; the corresponding cut-off frequency is determined by the loop bandwidth of LDO;
3) higher than certain frequency, PSRR falls off to large negative value again; the corresponding cut-off frequency is determined by the Cload and equivalent Rload.

Suppose pmos works in saturation region:
1) When Iload is high, the equivalent Rload is small, total LDO loop gain is small, because Rload serves as load of the pass transistor; thus reduces PSRR in low frequency region;
2) When Iload is relatively small, the equivalent Rload is high, p2 moves to lower frequency; at the same time, loop gain is high; thus makes LDO loop less stable.

How to test LDO?
1) shall not put ideal current source as load of LDO; the infinite Rout of the ideal current source is too unrealistic;
2) can put an equivalent Rload;
3) can put a current mirror as the load, with its Iout port connected to LDO output; Iref port can be connected to an ideal current source; the ideal current source can also be a pulse, to test the dynamics of LDO.

Reference:
Gabriel Rincon-Mora, Analog IC Design with Low-Dropout Regulators (LDOs), McGraw-Hill Professional; 1 edition (January 23, 2009)

Low dropout (LDO) regulator design