Analog IC design learning websites (to be amended)

http://www.idea2ic.com/
Useful sections:
* Frequently Used Javascript Calculators
* Cheat sheets for Analog IC Design

  

Analog IC design learning websites (to be amended)

Nwell of pmos is connected to vdd or its source?

If nwell is connected to source:

Pros:
1. no body effect, so vth is smaller, then the device can be turned on more, and the resulting gain can be large;

2. there is no mismatch due to vth variance from body effect (vth variance due to other reasons still exist);


Cons:
1. layout size is large, since different pmos cannot share the save nwell;

2. possible transient forward biasing of pn junction formed by nwell and p+ source, when the signal is sharp and the resistance between source and nwell is not small;

 

Nwell of pmos is connected to vdd or its source?

Low dropout (LDO) regulator design

LDO uses pmos as pass transistor. Why not nmos? If using nmos, output of the error amplifier op-amp applying on its gate may need to be very high, close to vdd. That makes such op-amp design difficult. When using pmos, the op-amp output is low, however, not to ground.

1) In light load (Iload is small), the pass pmos is working in saturation region;
2) When heavy load, the pass pmos may work in triode region, because Vgs has to be large to provide more current, and such  large Vgs may exceed Vds+Vth (both are fixed).

1) The dominant pole (p1) is usually inside the error amplifier op-amp, Miller frequency compensation formed by C or RC can be used, moving p1 to lower frequency, and/or providing a zero to cancel a pole's effect; p2 is usually at the LDO output; there is a high frequency pole due to the parasitic cap of pass pmos;
2) Alternatively, if the op-amp is one stage and/or does not have p1, frequency compensation can be done by putting C or RC across G and D of pass pmos, which can create p1. The parasitic caps inside op-amp thus create high frequency poles which are usually higher than p2, which is at the output of LDO.

Cload at the LDO output has a trade-off.
1) lager Cload can reduce the Vout ripple due to Iload switching;
2) smaller Cload moves p2 to higher frequency, making the LDO loop more stable.

PSRR over frequency usually has following shape:
1) at low frequency, PSRR is large negatively, e.g., -60 dB; the PSRR in this region is determined by the loop gain of LDO;
2) it rises to higher value in intermediate frequency, e.g., -20 dB; the corresponding cut-off frequency is determined by the loop bandwidth of LDO;
3) higher than certain frequency, PSRR falls off to large negative value again; the corresponding cut-off frequency is determined by the Cload and equivalent Rload.

Suppose pmos works in saturation region:
1) When Iload is high, the equivalent Rload is small, total LDO loop gain is small, because Rload serves as load of the pass transistor; thus reduces PSRR in low frequency region;
2) When Iload is relatively small, the equivalent Rload is high, p2 moves to lower frequency; at the same time, loop gain is high; thus makes LDO loop less stable.

How to test LDO?
1) shall not put ideal current source as load of LDO; the infinite Rout of the ideal current source is too unrealistic;
2) can put an equivalent Rload;
3) can put a current mirror as the load, with its Iout port connected to LDO output; Iref port can be connected to an ideal current source; the ideal current source can also be a pulse, to test the dynamics of LDO.

Reference:
Gabriel Rincon-Mora, Analog IC Design with Low-Dropout Regulators (LDOs), McGraw-Hill Professional; 1 edition (January 23, 2009)

Low dropout (LDO) regulator design

Bode Plot Basic Concepts and Practical Applications

Bode plot is usually drawn as an asymptotic approximation as connected straight lines; the bending points of the Bode plot correspond to the 3-dB point of the actual amplitude transfer function, which is also at a pole or a zero.

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The slope of amplitude Bode plot for voltage or current is Nx20dB/dec;

The phase Bode plot approaches Nx90 degrees after every pole/zero.

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Left-hand-plane (LHP) zero improves phase margin, by bending up both magnitude and phase; example of LHPZ is Rgd-and-Cgd-in-series induced zero, as 1/((gm^(-1)-Rgd)*Cgd), where Rgd is larger than gm^(-1);

Right-hand-plane (RHP) zero worsens phase margin, by bending up magnitude but bending down phase; example of RHPZ is Cgd induced zero, as 1/(gm^(-1)*Cgd).

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How to determine the frequency of a pole or a zero from a transfer function in simulation?

1. Look at the amplitude transfer function and locate the bending points; this is very difficult, when poles and zeros are close to each other;

2. Look at the phase transfer function: if the phase curves bends down from 0 to -90 degrees, there is a pole at -45 degrees; similar to zeros;

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How to determine which circuit node contributes to a pole or zero? 

1. Add a cap at one circuit node and the other node of the cap is grounded; increases the cap value, and observe the moving of the corresponding pole in the Bode plot;

2. When there are two nodes having C or RC cross them, modifies C or RC values and observe the moving of the corresponding zero in the Bode plot;

3. For the case that the signal passes several circuit nodes, one can look at the transfer function across two circuit nodes step by step, starting from the circuit input. For example, if the signal passes node A(input), B and C(output), one can first simulate transfer function between A and B to get the pole/zero contributed by A and B, then simulate transfer function between A and C so that one can isolate the extra pole/zero contributed only from C;

One can disconnect the following node connections (e.g., disconnecting C from the circuit) when analyzing the previous circuit nodes (A and B), which help prevent the loading effects from following circuit nodes;

Poles contributed by input/output nodes can be obtained by simulating the input/output impedance, whose imag part is contributed by cap.

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The above assumes that the poles and zeros are real value;

for the case that poles/zeros pair are complex, amplitude Bode plot bends extra -/+40dB/dec, and there are peaking around such complex poles/zeros; the phase Bode plot bends to extra -/+180 degrees.

Q: Do you ever see the case of complex zeros in circuit design?

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References:
http://www.swarthmore.edu/NatSci/echeeve1/Ref/LPSA/Bode/Bode.html

http://wikis.controltheorypro.com/index.php?title=Bode_Plot

http://en.wikibooks.org/wiki/Control_Systems/Bode_Plots

Bode Plot Basic Concepts and Practical Applications