Crystal oscillator design

1. Pierce oscillator is the most popular one; pros: easy startup; cons: needs to pins for external resonance connection;
1.1. Isolated Pierce oscillator is even better than simple Pierce oscillator;

2. Negative resistance: gme*Xce1*Xce2; here e means equivalent, indicating contribution not only from a single device, needing some (simple) calculation to obtain; can change gm or cap values to change Rneg;

3. Gain stage can be either inverter based or CS/CE mosfet/BJT with load (load can be current source, resistor or inductor);

4. Inverter based one is easy to design, however, it can perturb the power supply too much; its current consumption also varies over PVT;

5. Current-controlled mosfet can have precise control on current (and thus can be very low current), and does not perturb the power supply; however, it needs some calculation to check how much current it requires.

6. Designers shall check following:
1) Rneg and total loss, and make sure safety factor is moderate (not too large or too small);
2) Power burned by external resonator is within a limit;
3) Harmonics are properly filtered out before entering external resonator  (this post only discusses the case of crystal oscillator utilizing fundamental freq); otherwise, external resonator may have been excited at other freqs;
4) Device reliability: during transient, e.g., voltage cross mosfet oxide does not exceed certain value;
5) PSRR;
6) Phase noise;
7) Current consumption;
8) etc;

Ref:
Benjamin Parzen, Design of Crystal and Other Harmonic Oscillators

Crystal oscillator design

Vgs biasing of mosfet

1. The higher Vgs-Vth, the faster the speed, however, the lower gm/Ids;

2. To design a low-power circuit, Vgs shall be lower; for a high speed circuit, Vgs shall be higher. However, Vgs shall not be too high to saturate gm vs. Vgs, due to velocity saturation. When Vgs is too high, gm is saturated (or even reduces a little bit). fT = gm/(2*pi*Cgs). Cgs keeps almost constant when Vgs is high. So fT saturates though burning more current.

Vgs biasing of mosfet

CMFB of differential op-amp

1. It is preferred to use CMFB to apply to active load, not current source; poorly designed CMFB or wide PVT variation may turn off the current source controlled by CMFB, however, it can seldom shorten the active load;

2. If CMFB has to be applied to current source, the current source shall compose of a constant current source plus a CMFB controlled current source; thus the total current source can never be turned off;

3. The loop of CMFB is preferred to be short, not through too many devices; otherwise, too many low-freq poles can make it unstable; in the example of folded-cascode (FC) op-amp, if the CMFB is from the second-stage output and applied to the current source for input diff pair in the first-stage FC, the loop may be too long.

CMFB of differential op-amp

ESD protection design

1. ESD protection shall be considered beforehand, before designing individual circuit cells; ESD shall also be planned in the chip-level, e.g., where to put clamps (low impedance channels to divert ESD current);

2. Circuit simulation shall put ESD structures in the testbench to include the parasitics of ESD structures; putting ESD structures in the last minutes before tape-out is too late;

3. One shall also consider the effect from circuit cells to ESD structures;

4. ESD structures are categorized into break-down and non-break-down; break-down ones are non-SPICE-compatible, difficult or impossible to simulate using SPICE simulators, however they are smaller; non-break-down can be easily simulated using SPICE simulators, however they are usually larger.

5. Break-down ESD structures are usually found in standard cell library provided by foundry; they can serve as primary protection; they require multiple iteration of design, layout, tape-out and characterization; it is not recommended to design them by circuit designers; they can survive larger voltage;

6. Non-break-down ESD structures can be designed by circuit designers; they can serve as secondary protection, and can clamp the voltage to smaller value.

7. Break-down (BD) and non-break-down (NBD) structures can be the same device at different operational mode (e.g., forward-biased diode is NBD, reverse-biased one is BD), or using parasitic devices (using parasitic npn of ggNMOS is BD).

Ref:
Sanjay Dabral, and Timothy Maloney, Basic ESD and I/O Design

ESD protection design