ESD protection design

1. ESD protection shall be considered beforehand, before designing individual circuit cells; ESD shall also be planned in the chip-level, e.g., where to put clamps (low impedance channels to divert ESD current);

2. Circuit simulation shall put ESD structures in the testbench to include the parasitics of ESD structures; putting ESD structures in the last minutes before tape-out is too late;

3. One shall also consider the effect from circuit cells to ESD structures;

4. ESD structures are categorized into break-down and non-break-down; break-down ones are non-SPICE-compatible, difficult or impossible to simulate using SPICE simulators, however they are smaller; non-break-down can be easily simulated using SPICE simulators, however they are usually larger.

5. Break-down ESD structures are usually found in standard cell library provided by foundry; they can serve as primary protection; they require multiple iteration of design, layout, tape-out and characterization; it is not recommended to design them by circuit designers; they can survive larger voltage;

6. Non-break-down ESD structures can be designed by circuit designers; they can serve as secondary protection, and can clamp the voltage to smaller value.

7. Break-down (BD) and non-break-down (NBD) structures can be the same device at different operational mode (e.g., forward-biased diode is NBD, reverse-biased one is BD), or using parasitic devices (using parasitic npn of ggNMOS is BD).

Ref:
Sanjay Dabral, and Timothy Maloney, Basic ESD and I/O Design

ESD protection design