[Welcome to citing and linking to the pages of this blog] Summary of learning and practice of analog circuit, mixed-signal circuit and RF circuit designs, focused on their integrated circuit (IC) implementations. General knowledge learned from books, papers and practices are summarized. This blog also holds Job Hunting Guide, including interview questions, written by Fuding Ge.

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Contact email: rflover(at)gmail(dot)com {Announcement: This blog welcome the readers to submit your own tips, lifehacks, and knowledge in the Design of Analog IC, Mixed-Signal IC & RFIC (AMS/RFIC). The submitter shall be the author and copyright-holder of the article. The submitter will still keep the copyright after the submission. I will clearly indicate the copyright owner by using "©Author" after the article's title, for example, ©Mike Green. I will also provide a link at the first line of the article pointing to the submitter's website/blog. I can also provide the author's biography at the end of the article. The submitter can send me the article in .doc format to my email above. Your submitted articles will be subject to review before posting.}

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Showing posts with label Op-Amp. Show all posts
Showing posts with label Op-Amp. Show all posts

Monday, January 2, 2012

Analog IC design learning websites (to be amended)

http://www.idea2ic.com/
Useful sections:
* Frequently Used Javascript Calculators
* Cheat sheets for Analog IC Design

  
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Tuesday, May 11, 2010

Nwell of pmos is connected to vdd or its source?

If nwell is connected to source:

Pros:
1. no body effect, so vth is smaller, then the device can be turned on more, and the resulting gain can be large;

2. there is no mismatch due to vth variance from body effect (vth variance due to other reasons still exist);


Cons:
1. layout size is large, since different pmos cannot share the save nwell;

2. possible transient forward biasing of pn junction formed by nwell and p+ source, when the signal is sharp and the resistance between source and nwell is not small;

 
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Sunday, April 25, 2010

Two stage amplifier design tool in matlab

Using inversion coefficient.

http://www.coe.uncc.edu/~yyang29/


 
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Sunday, March 28, 2010

Vgs biasing of mosfet

1. The higher Vgs-Vth, the faster the speed, however, the lower gm/Ids;

2. To design a low-power circuit, Vgs shall be lower; for a high speed circuit, Vgs shall be higher. However, Vgs shall not be too high to saturate gm vs. Vgs, due to velocity saturation. When Vgs is too high, gm is saturated (or even reduces a little bit). fT = gm/(2*pi*Cgs). Cgs keeps almost constant when Vgs is high. So fT saturates though burning more current.
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CMFB of differential op-amp

1. It is preferred to use CMFB to apply to active load, not current source; poorly designed CMFB or wide PVT variation may turn off the current source controlled by CMFB, however, it can seldom shorten the active load;

2. If CMFB has to be applied to current source, the current source shall compose of a constant current source plus a CMFB controlled current source; thus the total current source can never be turned off;

3. The loop of CMFB is preferred to be short, not through too many devices; otherwise, too many low-freq poles can make it unstable; in the example of folded-cascode (FC) op-amp, if the CMFB is from the second-stage output and applied to the current source for input diff pair in the first-stage FC, the loop may be too long.


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