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* Cheat sheets for Analog IC Design
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Monday, January 2, 2012
Analog IC design learning websites (to be amended)
http://www.idea2ic.com/
Useful sections:
* Frequently Used Javascript Calculators
* Cheat sheets for Analog IC Design
Useful sections:
* Frequently Used Javascript Calculators
* Cheat sheets for Analog IC Design
Tuesday, May 11, 2010
Nwell of pmos is connected to vdd or its source?
If nwell is connected to source:
Pros:
1. no body effect, so vth is smaller, then the device can be turned on more, and the resulting gain can be large;
2. there is no mismatch due to vth variance from body effect (vth variance due to other reasons still exist);
Cons:
1. layout size is large, since different pmos cannot share the save nwell;
2. possible transient forward biasing of pn junction formed by nwell and p+ source, when the signal is sharp and the resistance between source and nwell is not small;
Pros:
1. no body effect, so vth is smaller, then the device can be turned on more, and the resulting gain can be large;
2. there is no mismatch due to vth variance from body effect (vth variance due to other reasons still exist);
Cons:
1. layout size is large, since different pmos cannot share the save nwell;
2. possible transient forward biasing of pn junction formed by nwell and p+ source, when the signal is sharp and the resistance between source and nwell is not small;
Thursday, May 6, 2010
Low dropout (LDO) regulator design
LDO uses pmos as pass transistor. Why not nmos? If using nmos, output of the error amplifier op-amp applying on its gate may need to be very high, close to vdd. That makes such op-amp design difficult. When using pmos, the op-amp output is low, however, not to ground.
1) In light load (Iload is small), the pass pmos is working in saturation region;
2) When heavy load, the pass pmos may work in triode region, because Vgs has to be large to provide more current, and such large Vgs may exceed Vds+Vth (both are fixed).
1) The dominant pole (p1) is usually inside the error amplifier op-amp, Miller frequency compensation formed by C or RC can be used, moving p1 to lower frequency, and/or providing a zero to cancel a pole's effect; p2 is usually at the LDO output; there is a high frequency pole due to the parasitic cap of pass pmos;
2) Alternatively, if the op-amp is one stage and/or does not have p1, frequency compensation can be done by putting C or RC across G and D of pass pmos, which can create p1. The parasitic caps inside op-amp thus create high frequency poles which are usually higher than p2, which is at the output of LDO.
Cload at the LDO output has a trade-off.
1) lager Cload can reduce the Vout ripple due to Iload switching;
2) smaller Cload moves p2 to higher frequency, making the LDO loop more stable.
PSRR over frequency usually has following shape:
1) at low frequency, PSRR is large negatively, e.g., -60 dB; the PSRR in this region is determined by the loop gain of LDO;
2) it rises to higher value in intermediate frequency, e.g., -20 dB; the corresponding cut-off frequency is determined by the loop bandwidth of LDO;
3) higher than certain frequency, PSRR falls off to large negative value again; the corresponding cut-off frequency is determined by the Cload and equivalent Rload.
Suppose pmos works in saturation region:
1) When Iload is high, the equivalent Rload is small, total LDO loop gain is small, because Rload serves as load of the pass transistor; thus reduces PSRR in low frequency region;
2) When Iload is relatively small, the equivalent Rload is high, p2 moves to lower frequency; at the same time, loop gain is high; thus makes LDO loop less stable.
How to test LDO?
1) shall not put ideal current source as load of LDO; the infinite Rout of the ideal current source is too unrealistic;
2) can put an equivalent Rload;
3) can put a current mirror as the load, with its Iout port connected to LDO output; Iref port can be connected to an ideal current source; the ideal current source can also be a pulse, to test the dynamics of LDO.
Reference:
Gabriel Rincon-Mora, Analog IC Design with Low-Dropout Regulators (LDOs), McGraw-Hill Professional; 1 edition (January 23, 2009)
1) In light load (Iload is small), the pass pmos is working in saturation region;
2) When heavy load, the pass pmos may work in triode region, because Vgs has to be large to provide more current, and such large Vgs may exceed Vds+Vth (both are fixed).
1) The dominant pole (p1) is usually inside the error amplifier op-amp, Miller frequency compensation formed by C or RC can be used, moving p1 to lower frequency, and/or providing a zero to cancel a pole's effect; p2 is usually at the LDO output; there is a high frequency pole due to the parasitic cap of pass pmos;
2) Alternatively, if the op-amp is one stage and/or does not have p1, frequency compensation can be done by putting C or RC across G and D of pass pmos, which can create p1. The parasitic caps inside op-amp thus create high frequency poles which are usually higher than p2, which is at the output of LDO.
Cload at the LDO output has a trade-off.
1) lager Cload can reduce the Vout ripple due to Iload switching;
2) smaller Cload moves p2 to higher frequency, making the LDO loop more stable.
PSRR over frequency usually has following shape:
1) at low frequency, PSRR is large negatively, e.g., -60 dB; the PSRR in this region is determined by the loop gain of LDO;
2) it rises to higher value in intermediate frequency, e.g., -20 dB; the corresponding cut-off frequency is determined by the loop bandwidth of LDO;
3) higher than certain frequency, PSRR falls off to large negative value again; the corresponding cut-off frequency is determined by the Cload and equivalent Rload.
Suppose pmos works in saturation region:
1) When Iload is high, the equivalent Rload is small, total LDO loop gain is small, because Rload serves as load of the pass transistor; thus reduces PSRR in low frequency region;
2) When Iload is relatively small, the equivalent Rload is high, p2 moves to lower frequency; at the same time, loop gain is high; thus makes LDO loop less stable.
How to test LDO?
1) shall not put ideal current source as load of LDO; the infinite Rout of the ideal current source is too unrealistic;
2) can put an equivalent Rload;
3) can put a current mirror as the load, with its Iout port connected to LDO output; Iref port can be connected to an ideal current source; the ideal current source can also be a pulse, to test the dynamics of LDO.
Reference:
Gabriel Rincon-Mora, Analog IC Design with Low-Dropout Regulators (LDOs), McGraw-Hill Professional; 1 edition (January 23, 2009)
Sunday, May 2, 2010
Bode Plot Basic Concepts and Practical Applications
Bode plot is usually drawn as an asymptotic approximation as connected straight lines; the bending points of the Bode plot correspond to the 3-dB point of the actual amplitude transfer function, which is also at a pole or a zero.
------------------------------------
The slope of amplitude Bode plot for voltage or current is Nx20dB/dec;
The phase Bode plot approaches Nx90 degrees after every pole/zero.
------------------------------------
Left-hand-plane (LHP) zero improves phase margin, by bending up both magnitude and phase; example of LHPZ is Rgd-and-Cgd-in-series induced zero, as 1/((gm^(-1)-Rgd)*Cgd), where Rgd is larger than gm^(-1);
Right-hand-plane (RHP) zero worsens phase margin, by bending up magnitude but bending down phase; example of RHPZ is Cgd induced zero, as 1/(gm^(-1)*Cgd).
---------------------------------------
How to determine the frequency of a pole or a zero from a transfer function in simulation?
1. Look at the amplitude transfer function and locate the bending points; this is very difficult, when poles and zeros are close to each other;
2. Look at the phase transfer function: if the phase curves bends down from 0 to -90 degrees, there is a pole at -45 degrees; similar to zeros;
-------------------------------------
How to determine which circuit node contributes to a pole or zero?
1. Add a cap at one circuit node and the other node of the cap is grounded; increases the cap value, and observe the moving of the corresponding pole in the Bode plot;
2. When there are two nodes having C or RC cross them, modifies C or RC values and observe the moving of the corresponding zero in the Bode plot;
3. For the case that the signal passes several circuit nodes, one can look at the transfer function across two circuit nodes step by step, starting from the circuit input. For example, if the signal passes node A(input), B and C(output), one can first simulate transfer function between A and B to get the pole/zero contributed by A and B, then simulate transfer function between A and C so that one can isolate the extra pole/zero contributed only from C;
One can disconnect the following node connections (e.g., disconnecting C from the circuit) when analyzing the previous circuit nodes (A and B), which help prevent the loading effects from following circuit nodes;
Poles contributed by input/output nodes can be obtained by simulating the input/output impedance, whose imag part is contributed by cap.
------------------------------------
The above assumes that the poles and zeros are real value;
for the case that poles/zeros pair are complex, amplitude Bode plot bends extra -/+40dB/dec, and there are peaking around such complex poles/zeros; the phase Bode plot bends to extra -/+180 degrees.
Q: Do you ever see the case of complex zeros in circuit design?
------------------------------------
References:
http://www.swarthmore.edu/NatSci/echeeve1/Ref/LPSA/Bode/Bode.html
http://wikis.controltheorypro.com/index.php?title=Bode_Plot
http://en.wikibooks.org/wiki/Control_Systems/Bode_Plots
------------------------------------
The slope of amplitude Bode plot for voltage or current is Nx20dB/dec;
The phase Bode plot approaches Nx90 degrees after every pole/zero.
------------------------------------
Left-hand-plane (LHP) zero improves phase margin, by bending up both magnitude and phase; example of LHPZ is Rgd-and-Cgd-in-series induced zero, as 1/((gm^(-1)-Rgd)*Cgd), where Rgd is larger than gm^(-1);
Right-hand-plane (RHP) zero worsens phase margin, by bending up magnitude but bending down phase; example of RHPZ is Cgd induced zero, as 1/(gm^(-1)*Cgd).
---------------------------------------
How to determine the frequency of a pole or a zero from a transfer function in simulation?
1. Look at the amplitude transfer function and locate the bending points; this is very difficult, when poles and zeros are close to each other;
2. Look at the phase transfer function: if the phase curves bends down from 0 to -90 degrees, there is a pole at -45 degrees; similar to zeros;
------------------------------------
The above assumes that the poles and zeros are real value;
for the case that poles/zeros pair are complex, amplitude Bode plot bends extra -/+40dB/dec, and there are peaking around such complex poles/zeros; the phase Bode plot bends to extra -/+180 degrees.
Q: Do you ever see the case of complex zeros in circuit design?
------------------------------------
References:
http://www.swarthmore.edu/NatSci/echeeve1/Ref/LPSA/Bode/Bode.html
http://wikis.controltheorypro.com/index.php?title=Bode_Plot
http://en.wikibooks.org/wiki/Control_Systems/Bode_Plots
Monday, April 26, 2010
Small softwares for analog IC design
http://www.analogeda.com/
includes:
* CornerTool "is a powerful tool for analog IC designers to run corner simulations with Spectre".
* JMOSCal is to calculate MOSFET curves, e.g., I-V. (Note: requires hspice)
includes:
* CornerTool "is a powerful tool for analog IC designers to run corner simulations with Spectre".
* JMOSCal is to calculate MOSFET curves, e.g., I-V. (Note: requires hspice)
Sunday, April 25, 2010
Tuesday, April 6, 2010
Some On-site Interview Questions (© Fuding Ge)
Almost everyone of the following questions was asked to me by an interviewer. Special thanks to Ge Wang at Maxim, Zhitao Jiang at Motorola.
1.If the following inverter biased in the middle of Vdd, what is the small signal gain? (Answer gm X ro)
2. Crossection diagram of the inverter (be able to draw the contact of power supply and ground)
3. From the crossection of the diagram, be able to draw the parasitic BJT leads to latch-up.
4 . How to prevent latch-up (do not forget guard ring, clampping circuits!)
5. Draw the layout of an inverter or NOR/NAND gate.
6. For the following source follower, what is its -3dB bandwidth? How about it stability?
7. In the following figure, if the two resisters are equal, what is its -3dB bandwidth? Compare its stability with that of a source follower.
8.For the following circuit, if the input is a rail-to-rail square wave, plot the wave after the inverter and vo.
9.For the following circuits, What is the gain? Using what technology to improve the matching of the input transistors? If the bias current increase, what happens to the gain? (Hit: Decrease!!!) What happens to the bandwidth? Replace the NMOS with npn BJT and PMOS with pnp BJT, answer the above questions.(Now gain remains constant with increasing biasing current!)
10. For the following circuits, answer the questions again. What are the advantages and disadvantages of these two amplifiers?
11. What are the effective resistance from source to drain of the following two transistors? (The value of the resistance is R). Answer: both of them are 1/gm.
12.What is the low frequency gain of the following circuits? The input is the input current Iin. Where does the dominant pole locate? How about the pole at node 1?
13.For the following circuit, the threshold voltage of the transistor is 0.7V. Vb1=1v, Vb2=2v, When Vin change from 5V to 0V, draw the current flow through the transistors VS Vin. (This question was supplied by Wang Ge)
14. For the following circuits, Vdd=5v, tell me what are Vo1 and Vo2 when Vin is 5V, 3V, 2.5V and 0V.
15. For the following circuit, what is the gain of Vout/Vin? Where is the Feedback and what is the function of feedback?
16. For the following circuits, the small signal input is i_in, the small signal output is v_out, what is the small signal output? What is the gain?
17. Figure out the Vout wave form of the following circuits:
Figure 1
Figure 2
Figure 3
Figure 4
Answer Hints: The basic concept to reply these kind of RC (or RLC) network questions is that: for C, it resistance is infinity when frequency=0 and 0 when frequency is infinity. (For L, its resistnace is 0 when frequency=0 while its resitance is infinity when frequency is infinity.
18. For the following circuit, at time 0, the switch switches from A to B, figure out the voltage wave form at B.
Note: this is a "classic" question. It was asked 10 years ago and I was asked this question just recently. You might be asked this question next time...
19. Fo the following circuit, what is the voltage value at A and B? (The Vt of the transistor is 1V).
[Problem 20 and 21 are not posted here.]
Note: Problem 20 and 21 are copied from the book edited by Jim Williams "The Art and Science of Analog Circuit Design
", published by Butterworth-Heinemann, 1995. ISBN 0-7506-9505-6, the chapter by Robert Reay, "A new graduate's guide to the analog interview". The chapter has 20 interview questions, but most of them are BJT problems. It may be helpful and interesting to read the chapter and even the wholw book. It is an INTERESTING book, though may be not very useful. It even includes a chapter by Richard P. Feynman (who is that guy? Come on, you should know him!).
", published by Butterworth-Heinemann, 1995. ISBN 0-7506-9505-6, the chapter by Robert Reay, "A new graduate's guide to the analog interview". The chapter has 20 interview questions, but most of them are BJT problems. It may be helpful and interesting to read the chapter and even the wholw book. It is an INTERESTING book, though may be not very useful. It even includes a chapter by Richard P. Feynman (who is that guy? Come on, you should know him!).
ABOUT DIGITAL CIRCUITS/VLSI DESIGN (© Fuding Ge)
Though you are applying for an analog circuits position, they often also ask you one or two digital/VLSI questions. To my experience, some basic logic gates such as NAND, NOR, XOR (XNOR) circuits are very important. Sometimes they ask you to use NAND NOR gates to realize the XOR function, some times they even ask you to use 8 transistor to realize this function. To my experience, you should read the whole textbook by Thomas A. DeMassa "Digital Integrated Circuits
" including those parts that talk about Flip-Flop. They often ask you a small question about State Machine or State Diagram. If you do not has the basic concepts of these concepts, read some books or take a course.
When I interviewed with Intel, they asked me to use some logic gates to realize a traffic light control problem (which I was unable to do in the specific time).
If they want to test your layout concepts, they may ask you to draw the layout of
NAND/NOR gate. Read the book "Principles of CMOS VLSI Design, A System Perspective
, Neil H.E. Weste, Kamran Eshraghian, AT&T, 1993" to get some "feeling".
At this point they may also ask you questions about ESD/Latchup, the above book is also good to refresh your memory.
[some more info of ESD protection]
Set-up and hold time are also very important concepts. You should know them for sure.
" including those parts that talk about Flip-Flop. They often ask you a small question about State Machine or State Diagram. If you do not has the basic concepts of these concepts, read some books or take a course.When I interviewed with Intel, they asked me to use some logic gates to realize a traffic light control problem (which I was unable to do in the specific time).
If they want to test your layout concepts, they may ask you to draw the layout of
NAND/NOR gate. Read the book "Principles of CMOS VLSI Design, A System Perspective
, Neil H.E. Weste, Kamran Eshraghian, AT&T, 1993" to get some "feeling".At this point they may also ask you questions about ESD/Latchup, the above book is also good to refresh your memory.
[some more info of ESD protection]
Set-up and hold time are also very important concepts. You should know them for sure.
Basic Questions (usually asked in phone interview) (© Fuding Ge)
1. Tell me a little bit about semiconductors (what is conductance and valence band? Fermi level? For n type semiconductor, what is the doping? Do you know how to say P and As in English?)
2. How does a pn junction works? (I know you know it, but could you tell other people clearly? Try it!!!, They ask you this question!). What is the depletion region? What is the build-in potential? What is the relation between these parameters with doping concentration and temperature? Remember the tempo of the build-in potential is about ?mV/K.
3. Tell me how MOSFET works. (Write it down in your own words and remember it !!!).
4. Tell me how BJT works. (Should I write down and remember it? Sure! But it is less asked). How does Vbe and Ic change with temperature?
5. Threshold voltage: If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?
6. Tell me what is Channel length modulation, what is Early effects and their physical origin.
7. Tell me what is short Channel effect.
8. For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?
9. How does a Bandgap Voltage reference work?
10. What is the ideal input and output resistance of a current source? How about voltage source? How to improve these parameters? (Cascode topology, use long channel transistors)
11. Tell me the parameters as many as possible you know that used to character an amplifier.
12. What are the two types of noise of MOSFET, how to eliminate them? (Thermal and Flicker).
2. How does a pn junction works? (I know you know it, but could you tell other people clearly? Try it!!!, They ask you this question!). What is the depletion region? What is the build-in potential? What is the relation between these parameters with doping concentration and temperature? Remember the tempo of the build-in potential is about ?mV/K.
3. Tell me how MOSFET works. (Write it down in your own words and remember it !!!).
4. Tell me how BJT works. (Should I write down and remember it? Sure! But it is less asked). How does Vbe and Ic change with temperature?
5. Threshold voltage: If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?
6. Tell me what is Channel length modulation, what is Early effects and their physical origin.
7. Tell me what is short Channel effect.
8. For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?
9. How does a Bandgap Voltage reference work?
10. What is the ideal input and output resistance of a current source? How about voltage source? How to improve these parameters? (Cascode topology, use long channel transistors)
11. Tell me the parameters as many as possible you know that used to character an amplifier.
12. What are the two types of noise of MOSFET, how to eliminate them? (Thermal and Flicker).
Monday, April 5, 2010
Some Good Books for Analog IC Design (©Fuding Ge)
Some Good Books:
(Pay more attention on CMOS than BJT books)
• CMOS Circuit design, CMOS Circuit Design, Layout, and Simulation, Revised Second Edition
, R Jacob Baker, Harry W. Li and David E. Boyce, IEEE Press, 1998 (university of Idaho), TK7871.99.M44B351998. A good book to read. You may not be able to learn lot of theory, but you do learn some circuits you can use. It is a ENGINEER book.
• Analog Integrated Circuit Design
, David Johns, Ken Martin, University of Toronto, John Wiley, Inc. A must read classic book on CMOS. Good circuit cook book and circuit theory. The part of Switched-capacitor PLL parts are very good and you must know it.
• Microelectronic Circuits
(the latest edition is 4th). Adel S. Sedra, Kenneth C. Smith, Oxford, 1998 (University of Toronto). A very good book! It is for undergraduates, easy to understand and the summery is very good and equation is very insightful. A must-read book before interview.
• CMOS Analog Circuit Design
, Phillip E. Allen and Douglas R. Holberg, Published in 1987. A little older but still worth to read. (It has a later edition (2002 ?, but I have not found time to read yet).
• Design of analog CMOS Integrated Circuits
, Behzad Razavi, McGraw-Hill, 2001. A textbook used by many schools. It helps you understanding lot of the circuits, but too simple to use in real design. I should say it is a very good theory book. Not ENGINEER book. Anyway IT ALL BEGINS FROM MAXWELL'S
EQUATIONS, RIGHT?
• Principles of CMOS VLSI Design, A System Perspective, Neil H.E. Weste, Kamran Eshraghian, AT&T, 1993
• Fundamental of Logic Design, (Any textbook is OK)
(Pay more attention on CMOS than BJT books)
• CMOS Circuit design, CMOS Circuit Design, Layout, and Simulation, Revised Second Edition
, R Jacob Baker, Harry W. Li and David E. Boyce, IEEE Press, 1998 (university of Idaho), TK7871.99.M44B351998. A good book to read. You may not be able to learn lot of theory, but you do learn some circuits you can use. It is a ENGINEER book.• Analog Integrated Circuit Design
, David Johns, Ken Martin, University of Toronto, John Wiley, Inc. A must read classic book on CMOS. Good circuit cook book and circuit theory. The part of Switched-capacitor PLL parts are very good and you must know it.• Microelectronic Circuits
(the latest edition is 4th). Adel S. Sedra, Kenneth C. Smith, Oxford, 1998 (University of Toronto). A very good book! It is for undergraduates, easy to understand and the summery is very good and equation is very insightful. A must-read book before interview.• CMOS Analog Circuit Design
, Phillip E. Allen and Douglas R. Holberg, Published in 1987. A little older but still worth to read. (It has a later edition (2002 ?, but I have not found time to read yet).• Design of analog CMOS Integrated Circuits
, Behzad Razavi, McGraw-Hill, 2001. A textbook used by many schools. It helps you understanding lot of the circuits, but too simple to use in real design. I should say it is a very good theory book. Not ENGINEER book. Anyway IT ALL BEGINS FROM MAXWELL'SEQUATIONS, RIGHT?
• Principles of CMOS VLSI Design, A System Perspective
, Neil H.E. Weste, Kamran Eshraghian, AT&T, 1993• Fundamental of Logic Design, (Any textbook is OK)
Some Basic Concepts of Analog IC Design (©Fuding Ge)
Some Basic Concepts you should know before job hounting:
You should grasp the following concepts:
• Gain, (how to improve gain?)
• Bandwidth, (how to improve bandwidth?)
• Feedback,(Stability is a must ask question! Know pole, zero, gain and phase margin!)
• Slew rate,(How to improve slew rate?)
• Offset,(how to eliminate offset? Chopper stabilized circuits, autozero)
• Noise,(what is thermal, flick, shot noise? What are the noises of BJT and MOSFET? (Tell me one way to reduce flick noise)
• Compensation (what is Miller, lead and Lag compensation? Know what is Miller Effects).
• Layout (centroid, interdigital) (how to improve the match of current mirror, differential pairs?
Remember: Same Structure (poly-poly not one is poly-poly another is poly-metal), same temperature, same Shape and size, same orientation (current flow parallel), same surroundings(dummy transistors) and Common-centroid geometry (fingers, interdigitated fingers, what is the purpose of breaking into fingers?))
Suggested Reading: Koen Lampaert, Georges Gielen and Willy Sansen, Analog Layout Generation for Performance and Manufacturability, Kluwer Academic Publishers, 1999
• Thermal resistance (basic calculation).
• Filter
• Oscillator
• Peak detector
• Frequency divider
• Bandgap Reference
• You also need to know a little bit about testing, for example DFT.
(I will later provide more details for each of the concepts.)
Recommended Courses to Take for Analog IC Design (©Fuding Ge)
Courses:
You must take the following courses:
• Device physics
• Analog circuits analysis and design
• Advanced analog IC design
• A/D converter
• Digital circuits analysis
• VLSI design
• Filter design
• PLL design
• RF circuit design
You better to take the following courses if Available:
• Semiconductor and device characterization
• VLSI Architecture
• Computer architecture
• VHDL
• Logic Design
(I will find time to provide link to openly accessed course websites/notes later.)
You must take the following courses:
• Device physics
• Analog circuits analysis and design
• Advanced analog IC design
• A/D converter
• Digital circuits analysis
• VLSI design
• Filter design
• PLL design
• RF circuit design
You better to take the following courses if Available:
• Semiconductor and device characterization
• VLSI Architecture
• Computer architecture
• VHDL
• Logic Design
(I will find time to provide link to openly accessed course websites/notes later.)
Will post Job Hunting Guide, including interview questions, written by Fuding Ge
As I found out recently, that Fuding Ge's personal website (http://geocities.com/fudingge/jobguide.html) originally held on Yahoo Geocities cannot be accessed, since Yahoo does not provide service of personal website anymore.
I contacted Fuding Ge, and he allows me to post his Job Hunting Guide, including his interview questions, on my blog. I will do so soon. Please note that all the materials written by Fuding Ge are copyrighted by him, as originally indicated in his website.
Furthermore, I plan to elaborate on his Job Hunting Guide, and also answer his interview questions one by one, in my future blog posts.
I contacted Fuding Ge, and he allows me to post his Job Hunting Guide, including his interview questions, on my blog. I will do so soon. Please note that all the materials written by Fuding Ge are copyrighted by him, as originally indicated in his website.
Furthermore, I plan to elaborate on his Job Hunting Guide, and also answer his interview questions one by one, in my future blog posts.
Sunday, April 4, 2010
Free device model parameters for analog IC simulation - Predictive Technology Model, and etc.
http://www.eas.asu.edu/~ptm/
http://ptm.asu.edu/
Though the device parameters are not measured from the real devices, they can be used for simulation (within reasonable tolerance?).
Will read it for more details.
============================
Another related website http://www.mos-ak.org/
At its "Modeling Links", there are several related links to device modeling websites.
============================
In http://www.idea2ic.com/index.html, search for "BSIM4 simplified", you can also find information of device modeling, including the comparison between various device parameters with different lengths (180nm down to 22nm) in PDF.
===========================
1um and 50nm MOSFET models, provided by R. Jacob Baker:
http://cmosedu.com/cmos1/cmosedu_models.txt
http://ptm.asu.edu/
Though the device parameters are not measured from the real devices, they can be used for simulation (within reasonable tolerance?).
Will read it for more details.
============================
Another related website http://www.mos-ak.org/
At its "Modeling Links", there are several related links to device modeling websites.
============================
In http://www.idea2ic.com/index.html, search for "BSIM4 simplified", you can also find information of device modeling, including the comparison between various device parameters with different lengths (180nm down to 22nm) in PDF.
===========================
1um and 50nm MOSFET models, provided by R. Jacob Baker:
http://cmosedu.com/cmos1/cmosedu_models.txt
Sunday, March 28, 2010
Crystal oscillator design
1. Pierce oscillator is the most popular one; pros: easy startup; cons: needs to pins for external resonance connection;
1.1. Isolated Pierce oscillator is even better than simple Pierce oscillator;
2. Negative resistance: gme*Xce1*Xce2; here e means equivalent, indicating contribution not only from a single device, needing some (simple) calculation to obtain; can change gm or cap values to change Rneg;
3. Gain stage can be either inverter based or CS/CE mosfet/BJT with load (load can be current source, resistor or inductor);
4. Inverter based one is easy to design, however, it can perturb the power supply too much; its current consumption also varies over PVT;
5. Current-controlled mosfet can have precise control on current (and thus can be very low current), and does not perturb the power supply; however, it needs some calculation to check how much current it requires.
6. Designers shall check following:
1) Rneg and total loss, and make sure safety factor is moderate (not too large or too small);
2) Power burned by external resonator is within a limit;
3) Harmonics are properly filtered out before entering external resonator (this post only discusses the case of crystal oscillator utilizing fundamental freq); otherwise, external resonator may have been excited at other freqs;
4) Device reliability: during transient, e.g., voltage cross mosfet oxide does not exceed certain value;
5) PSRR;
6) Phase noise;
7) Current consumption;
8) etc;
Ref:
Benjamin Parzen, Design of Crystal and Other Harmonic Oscillators
1.1. Isolated Pierce oscillator is even better than simple Pierce oscillator;
2. Negative resistance: gme*Xce1*Xce2; here e means equivalent, indicating contribution not only from a single device, needing some (simple) calculation to obtain; can change gm or cap values to change Rneg;
3. Gain stage can be either inverter based or CS/CE mosfet/BJT with load (load can be current source, resistor or inductor);
4. Inverter based one is easy to design, however, it can perturb the power supply too much; its current consumption also varies over PVT;
5. Current-controlled mosfet can have precise control on current (and thus can be very low current), and does not perturb the power supply; however, it needs some calculation to check how much current it requires.
6. Designers shall check following:
1) Rneg and total loss, and make sure safety factor is moderate (not too large or too small);
2) Power burned by external resonator is within a limit;
3) Harmonics are properly filtered out before entering external resonator (this post only discusses the case of crystal oscillator utilizing fundamental freq); otherwise, external resonator may have been excited at other freqs;
4) Device reliability: during transient, e.g., voltage cross mosfet oxide does not exceed certain value;
5) PSRR;
6) Phase noise;
7) Current consumption;
8) etc;
Ref:
Benjamin Parzen, Design of Crystal and Other Harmonic Oscillators
Vgs biasing of mosfet
1. The higher Vgs-Vth, the faster the speed, however, the lower gm/Ids;
2. To design a low-power circuit, Vgs shall be lower; for a high speed circuit, Vgs shall be higher. However, Vgs shall not be too high to saturate gm vs. Vgs, due to velocity saturation. When Vgs is too high, gm is saturated (or even reduces a little bit). fT = gm/(2*pi*Cgs). Cgs keeps almost constant when Vgs is high. So fT saturates though burning more current.
2. To design a low-power circuit, Vgs shall be lower; for a high speed circuit, Vgs shall be higher. However, Vgs shall not be too high to saturate gm vs. Vgs, due to velocity saturation. When Vgs is too high, gm is saturated (or even reduces a little bit). fT = gm/(2*pi*Cgs). Cgs keeps almost constant when Vgs is high. So fT saturates though burning more current.
CMFB of differential op-amp
1. It is preferred to use CMFB to apply to active load, not current source; poorly designed CMFB or wide PVT variation may turn off the current source controlled by CMFB, however, it can seldom shorten the active load;
2. If CMFB has to be applied to current source, the current source shall compose of a constant current source plus a CMFB controlled current source; thus the total current source can never be turned off;
3. The loop of CMFB is preferred to be short, not through too many devices; otherwise, too many low-freq poles can make it unstable; in the example of folded-cascode (FC) op-amp, if the CMFB is from the second-stage output and applied to the current source for input diff pair in the first-stage FC, the loop may be too long.
ESD protection design
1. ESD protection shall be considered beforehand, before designing individual circuit cells; ESD shall also be planned in the chip-level, e.g., where to put clamps (low impedance channels to divert ESD current);
2. Circuit simulation shall put ESD structures in the testbench to include the parasitics of ESD structures; putting ESD structures in the last minutes before tape-out is too late;
3. One shall also consider the effect from circuit cells to ESD structures;
4. ESD structures are categorized into break-down and non-break-down; break-down ones are non-SPICE-compatible, difficult or impossible to simulate using SPICE simulators, however they are smaller; non-break-down can be easily simulated using SPICE simulators, however they are usually larger.
5. Break-down ESD structures are usually found in standard cell library provided by foundry; they can serve as primary protection; they require multiple iteration of design, layout, tape-out and characterization; it is not recommended to design them by circuit designers; they can survive larger voltage;
6. Non-break-down ESD structures can be designed by circuit designers; they can serve as secondary protection, and can clamp the voltage to smaller value.
7. Break-down (BD) and non-break-down (NBD) structures can be the same device at different operational mode (e.g., forward-biased diode is NBD, reverse-biased one is BD), or using parasitic devices (using parasitic npn of ggNMOS is BD).
Ref:
Sanjay Dabral, and Timothy Maloney, Basic ESD and I/O Design
2. Circuit simulation shall put ESD structures in the testbench to include the parasitics of ESD structures; putting ESD structures in the last minutes before tape-out is too late;
3. One shall also consider the effect from circuit cells to ESD structures;
4. ESD structures are categorized into break-down and non-break-down; break-down ones are non-SPICE-compatible, difficult or impossible to simulate using SPICE simulators, however they are smaller; non-break-down can be easily simulated using SPICE simulators, however they are usually larger.
5. Break-down ESD structures are usually found in standard cell library provided by foundry; they can serve as primary protection; they require multiple iteration of design, layout, tape-out and characterization; it is not recommended to design them by circuit designers; they can survive larger voltage;
6. Non-break-down ESD structures can be designed by circuit designers; they can serve as secondary protection, and can clamp the voltage to smaller value.
7. Break-down (BD) and non-break-down (NBD) structures can be the same device at different operational mode (e.g., forward-biased diode is NBD, reverse-biased one is BD), or using parasitic devices (using parasitic npn of ggNMOS is BD).
Ref:
Sanjay Dabral, and Timothy Maloney, Basic ESD and I/O Design
Tuesday, July 14, 2009
Shall always synchronize external input by internal clock
Monday, July 13, 2009
Free SPICE simulator from TI
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