includes:
* CornerTool "is a powerful tool for analog IC designers to run corner simulations with Spectre".
* JMOSCal is to calculate MOSFET curves, e.g., I-V. (Note: requires hspice)
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Monday, April 26, 2010
Small softwares for analog IC design
http://www.analogeda.com/
includes:
* CornerTool "is a powerful tool for analog IC designers to run corner simulations with Spectre".
* JMOSCal is to calculate MOSFET curves, e.g., I-V. (Note: requires hspice)
includes:
* CornerTool "is a powerful tool for analog IC designers to run corner simulations with Spectre".
* JMOSCal is to calculate MOSFET curves, e.g., I-V. (Note: requires hspice)
Sunday, April 25, 2010
Tuesday, April 6, 2010
Some On-site Interview Questions (© Fuding Ge)
Almost everyone of the following questions was asked to me by an interviewer. Special thanks to Ge Wang at Maxim, Zhitao Jiang at Motorola.
1.If the following inverter biased in the middle of Vdd, what is the small signal gain? (Answer gm X ro)
2. Crossection diagram of the inverter (be able to draw the contact of power supply and ground)
3. From the crossection of the diagram, be able to draw the parasitic BJT leads to latch-up.
4 . How to prevent latch-up (do not forget guard ring, clampping circuits!)
5. Draw the layout of an inverter or NOR/NAND gate.
6. For the following source follower, what is its -3dB bandwidth? How about it stability?
7. In the following figure, if the two resisters are equal, what is its -3dB bandwidth? Compare its stability with that of a source follower.
8.For the following circuit, if the input is a rail-to-rail square wave, plot the wave after the inverter and vo.
9.For the following circuits, What is the gain? Using what technology to improve the matching of the input transistors? If the bias current increase, what happens to the gain? (Hit: Decrease!!!) What happens to the bandwidth? Replace the NMOS with npn BJT and PMOS with pnp BJT, answer the above questions.(Now gain remains constant with increasing biasing current!)
10. For the following circuits, answer the questions again. What are the advantages and disadvantages of these two amplifiers?
11. What are the effective resistance from source to drain of the following two transistors? (The value of the resistance is R). Answer: both of them are 1/gm.
12.What is the low frequency gain of the following circuits? The input is the input current Iin. Where does the dominant pole locate? How about the pole at node 1?
13.For the following circuit, the threshold voltage of the transistor is 0.7V. Vb1=1v, Vb2=2v, When Vin change from 5V to 0V, draw the current flow through the transistors VS Vin. (This question was supplied by Wang Ge)
14. For the following circuits, Vdd=5v, tell me what are Vo1 and Vo2 when Vin is 5V, 3V, 2.5V and 0V.
15. For the following circuit, what is the gain of Vout/Vin? Where is the Feedback and what is the function of feedback?
16. For the following circuits, the small signal input is i_in, the small signal output is v_out, what is the small signal output? What is the gain?
17. Figure out the Vout wave form of the following circuits:
Figure 1
Figure 2
Figure 3
Figure 4
Answer Hints: The basic concept to reply these kind of RC (or RLC) network questions is that: for C, it resistance is infinity when frequency=0 and 0 when frequency is infinity. (For L, its resistnace is 0 when frequency=0 while its resitance is infinity when frequency is infinity.
18. For the following circuit, at time 0, the switch switches from A to B, figure out the voltage wave form at B.
Note: this is a "classic" question. It was asked 10 years ago and I was asked this question just recently. You might be asked this question next time...
19. Fo the following circuit, what is the voltage value at A and B? (The Vt of the transistor is 1V).
[Problem 20 and 21 are not posted here.]
Note: Problem 20 and 21 are copied from the book edited by Jim Williams "The Art and Science of Analog Circuit Design
", published by Butterworth-Heinemann, 1995. ISBN 0-7506-9505-6, the chapter by Robert Reay, "A new graduate's guide to the analog interview". The chapter has 20 interview questions, but most of them are BJT problems. It may be helpful and interesting to read the chapter and even the wholw book. It is an INTERESTING book, though may be not very useful. It even includes a chapter by Richard P. Feynman (who is that guy? Come on, you should know him!).
", published by Butterworth-Heinemann, 1995. ISBN 0-7506-9505-6, the chapter by Robert Reay, "A new graduate's guide to the analog interview". The chapter has 20 interview questions, but most of them are BJT problems. It may be helpful and interesting to read the chapter and even the wholw book. It is an INTERESTING book, though may be not very useful. It even includes a chapter by Richard P. Feynman (who is that guy? Come on, you should know him!).
ABOUT DIGITAL CIRCUITS/VLSI DESIGN (© Fuding Ge)
Though you are applying for an analog circuits position, they often also ask you one or two digital/VLSI questions. To my experience, some basic logic gates such as NAND, NOR, XOR (XNOR) circuits are very important. Sometimes they ask you to use NAND NOR gates to realize the XOR function, some times they even ask you to use 8 transistor to realize this function. To my experience, you should read the whole textbook by Thomas A. DeMassa "Digital Integrated Circuits
" including those parts that talk about Flip-Flop. They often ask you a small question about State Machine or State Diagram. If you do not has the basic concepts of these concepts, read some books or take a course.
When I interviewed with Intel, they asked me to use some logic gates to realize a traffic light control problem (which I was unable to do in the specific time).
If they want to test your layout concepts, they may ask you to draw the layout of
NAND/NOR gate. Read the book "Principles of CMOS VLSI Design, A System Perspective
, Neil H.E. Weste, Kamran Eshraghian, AT&T, 1993" to get some "feeling".
At this point they may also ask you questions about ESD/Latchup, the above book is also good to refresh your memory.
[some more info of ESD protection]
Set-up and hold time are also very important concepts. You should know them for sure.
" including those parts that talk about Flip-Flop. They often ask you a small question about State Machine or State Diagram. If you do not has the basic concepts of these concepts, read some books or take a course.When I interviewed with Intel, they asked me to use some logic gates to realize a traffic light control problem (which I was unable to do in the specific time).
If they want to test your layout concepts, they may ask you to draw the layout of
NAND/NOR gate. Read the book "Principles of CMOS VLSI Design, A System Perspective
, Neil H.E. Weste, Kamran Eshraghian, AT&T, 1993" to get some "feeling".At this point they may also ask you questions about ESD/Latchup, the above book is also good to refresh your memory.
[some more info of ESD protection]
Set-up and hold time are also very important concepts. You should know them for sure.
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